unisonic technologies co., ltd ls3718 cmos ic www.unisonic.com.tw 1 of 8 copyright ? 2015 unisonic technologies co., ltd qw-r121-015.b 20-bit serial to parallel converter ? description the utc ls3718 is a 20-bit serial to parallel converter utilizing cmos technology. it is incorporates control circuit, shift register, latch and driver into a single ship. it is suitable for mcu interface. the effective interface assignment of mpu is available as the connection between utc ls3718 and mpu is required only 4 lines. the device is designed to operate up to 5mhz. when the serial data input to the data terminal and the data is output from parallel output buffer through serial in paral lel out shift register and parallel data latches. the data can through the shift regi ster serial output to the so terminal. therefore the utc ls3718 can cascade connection to expand the output data number. the hysteresis input circuit realizes wide noise margin and the high drive-ability output buffer ( 25ma) can drive led directly. ? features * 20-bit serial in parallel out * cascade connection * operating voltage 5v10% * hysteresis input 0.5v typ * output current 25ma * operating frequency 5mhz or more ? ordering information ordering number package packing LS3718G-S28-R sop-28 tape reel ? marking
ls3718 cmos ic unisonic technologies co., ltd 2 of 8 www.unisonic.com.tw qw-r121-015.b ? pin configuration p9 p10 p11 p12 p13 p14 v ss p15 p16 p17 p18 p19 p20 so 1 2 3 4 5 6 7 8 9 10 11 12 13 14 v dd p8 p7 p6 p5 p4 p3 v ss p2 p1 clr stb clk data 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ? pin description pin no pin name i/o description 1 p9 o parallel data output pin 9 2 p10 o parallel data output pin 10 3 p11 o parallel data output pin 11 4 p12 o parallel data output pin 12 5 p13 o parallel data output pin 13 6 p14 o parallel data output pin 14 7 v ss gnd 8 p15 o parallel data output pin 15 9 p16 o parallel data output pin 16 10 p17 o parallel data output pin 17 11 p18 o parallel data output pin 18 12 p19 o parallel data output pin 19 13 p20 o parallel data output pin 20 14 so o serial data output pin 15 data i serial data input pin 16 clk i clock signal input pin 17 stb i data strobe, low actived 18 clr i data reset, low actived 19 p1 o parallel data output pin 1 20 p2 o parallel data output pin 2 21 v ss gnd 22 p3 o parallel data output pin 3 23 p4 o parallel data output pin 4 24 p5 o parallel data output pin 5 25 p6 o parallel data output pin 6 26 p7 o parallel data output pin 7 27 p8 o parallel data output pin 8 28 v dd power supply
ls3718 cmos ic unisonic technologies co., ltd 3 of 8 www.unisonic.com.tw qw-r121-015.b ? block diagram control shift register latch driver data clk stb clr p1~p20 so
ls3718 cmos ic unisonic technologies co., ltd 4 of 8 www.unisonic.com.tw qw-r121-015.b ? absolute maximum ratings (t a =25c, unless otherwise specified) parameter symbol ratings unit supply voltage v dd -0.5~+7.0 v input voltage v in v ss -0.5~v dd +0.5 v output voltage v out v ss -0.5~v dd +0.5 v output current i out 25 ma power dissipation p d 500 mw junction temperature t j +125 c operating temperature t opr -25 ~ +85 c storage temperature t stg -40 ~ +150 c note: absolute maximum ratings are those values beyond which the device could be permanently damaged. absolute maximum ratings are stress ratings only and functional device oper ation is not implied. ? electrical characteristics (v dd =4.5~5.5v, v ss =0v, t a =25c, unless otherwise specified) parameter symbol test conditions min typ max unit operating voltage v dd 4.5 5.5 v operating current i s v ih =v dd , v il =v ss 0.1 ma input leakage current i i(leak) v in =0~v dd -10 10 a high-level v ih 0.7v dd v dd v input voltage low-level v il v ss 0.3 v dd high-level v oh i oh =-0.4ma 4.0 4.97 v dd v output voltage low-level v ol i ol =+3.2ma so terminal v ss 0.11 0.4 i oh =-25ma v dd -1.5 v dd -0.5 v dd v i oh =-15ma v dd -1.0 v dd -0.3 v dd high-level v ohp i oh =-10ma v dd -0.5 v dd -0.2 v dd i ol =+25ma v ss 0.5 1.5 v i ol =+15ma v ss 0.3 0.8 output voltage low-level v olp i ol =+10ma p1~p20 terminals (note) v ss 0.2 0.4 note: specified value represent output current per pin. when use, total curr ent consideration and less than power dissipation rating operation should be required. ? switching characteristics (v dd =4.5~5.5v, v ss =0v, t a =-20~75c, unless otherwise specified) parameter symbol test conditions min typ max unit data set-up time t sd data-clk 20 ns data hold time t hd clk-data 20 ns set-up time t sstb stb -clk 30 ns hold time t hstb clk- stb 30 ns t pd o clk-so 70 ns t pd pck clk-p1~p20 100 ns t pd pstb stb -p1~p2 80 ns output delay time t pd pclr clr -p1~p20 80 ns max. operating frequency f max 5 mhz note: c out =50pf
ls3718 cmos ic unisonic technologies co., ltd 5 of 8 www.unisonic.com.tw qw-r121-015.b ? switching characteristics test waveform f max t sd t hd t hstb t sstb t pd o t pd pck h t pd stb t pd pclr clk data stb clk so clk stb p1~p 20 clk stb p1~p 20 clr data p1~p 20
ls3718 cmos ic unisonic technologies co., ltd 6 of 8 www.unisonic.com.tw qw-r121-015.b ? function description reset when the clr terminal is "l" level, all latches are reset and all of parallel output are "l" level. normally, the clr terminal should be "h" level. data transmission when the stb terminal is "h" level and input the clock signal to the clk terminal, the serial data input the data terminal and shift in the shift register by sync hronizing at rising edge of the clock signal. when the stb terminal is changed to "l" level, the data in the shift register are transferred to the latch. even if the stb terminal is "l" level, the input clock signal shift the data in the shift regist er, therefore, the clock signal controlled is needed. cascade connection the serial data input from data terminal and output from t he so terminal through internal shift register unrelated to the clr and stb status. furthermore, the 4 input terminals have a hysteresis characte ristic by using the schmitt trigger structure to decrease the noise. clk stb clr description x x l all latch are reset (the data in the shift r egister is not change). all of parallel outputs are "l". h h the serial data input from data terminal to the shift register (the data in the latch is not change). l h the data in the shift register transfer to the latch. and t he data in the latch output from the parallel output. l h the clk input in the stb ="l" and clr ="h" state, the data shift in the shift register and latched data also change in accordance with the shift register. note: x: don?t care
ls3718 cmos ic unisonic technologies co., ltd 7 of 8 www.unisonic.com.tw qw-r121-015.b ? timing chart
ls3718 cmos ic unisonic technologies co., ltd 8 of 8 www.unisonic.com.tw qw-r121-015.b ? typical application circuit cascade connection utc ls3718 so p1~p20 data clk stb clr utc ls3718 mpu so p1~p20 data clk stb clr utc assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all utc products described or contained herein. utc products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice.
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